Re: [sv-bc] port-size mismatch warning

I don't see anything in the LRM about such a warning being required
here, but a warning would be helpful.  Here's a 1995-style test case --

module TOP(test_bit);
  output test_bit;
  wire o2, o3;
  BOT#(2) bot2(.in(2'b11 + 2'b01 >> 1), .out(o2));
  BOT#(3) bot3(.in(2'b11 + 2'b01 >> 1), .out(o3));
  assign test_bit = o2 != o3;
  initial #1 $display("test_bit == %b", test_bit);
endmodule

module BOT(in, out);
  parameter N = 0;
  input [N-1:0] in;
  output out;
  assign out = in[1];
endmodule
 
[This message is in reply to http://www.eda-stds.org/sv-bc/hm/5040.html
.]

-- Brad