Date: Mon Sep 04 2006 - 07:26:44 PDT
19.11.2 says, "Verilog has always permitted instantiation of modules using named port connections ... The variables connected to the instance ports must be the same size, or a port-size mismatch warning shall be reported." This seems to be referring to a warning which is assumed to be required in 1364 and not a new requirement. Similarly, 19.11.1 says, "Verilog has always permitted instantiation of modules using positional port connections ... As long as the connecting variables are ordered correctly and are the same size as the instance ports to which they are connected, there shall be no warnings and the simulation shall work as expected." and again seems to be assuming that same requirement in 1364. I did not find, nor remember such a requirement. Is it there? Note that if there were such a requirement, it would also occur if a port were explicitly described as unconnected, as in ".port()". Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
