RE: [sv-bc] port-size mismatch warning

Hi, Shalom -

Another interesting catch! Some people have gone over the Verilog LRM 
with a fine-toothed comb. I think you are using a squeegee!  :-)

To my knowledge, all major implementations warn regarding port-size 
mismatch and port-size mismatches are almost always errors. I believe 
we should add this as one of the rules under clause 12.3.9 in the 
1364 LRM. I may have been responsible for the offending language in 
the 1800 standard. My votes below:

At 02:45 AM 9/6/2006, Bresticker, Shalom wrote:
>Sure such warnings are useful, but there are dozens of useful warnings.
>The vast majority are left up to the tool implementors.
>
>First question is, is this already required in 1364?

Perhaps not but I believe we should add it. All vendors seem to have 
this in place anyway.

>Second is, is this required in 1800 deliberately or by mistake?

I believe this was a mistaken assumption (again, perhaps on my part 
based on long experience with multiple Verilog simulators).

>Third is, should this be required by the standard?

I would like to see this added as a requirement. It is useful and 
already in place.

Regards - Cliff


>I don't know for sure, but I think the answers are: no, by mistake, no.
>
>Shalom
>
>
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
>On
> > Behalf Of Brad Pierce
> > Sent: Wednesday, September 06, 2006 8:03 AM
> > To: sv-bc@server.eda-stds.org
> > Subject: Re: [sv-bc] port-size mismatch warning
> >
> > I don't see anything in the LRM about such a warning being required
> > here, but a warning would be helpful.  Here's a 1995-style test case
>--
> >
> > module TOP(test_bit);
> >   output test_bit;
> >   wire o2, o3;
> >   BOT#(2) bot2(.in(2'b11 + 2'b01 >> 1), .out(o2));
> >   BOT#(3) bot3(.in(2'b11 + 2'b01 >> 1), .out(o3));
> >   assign test_bit = o2 != o3;
> >   initial #1 $display("test_bit == %b", test_bit);
> > endmodule
> >
> > module BOT(in, out);
> >   parameter N = 0;
> >   input [N-1:0] in;
> >   output out;
> >   assign out = in[1];
> > endmodule
> >
> > [This message is in reply to
>http://www.eda-stds.org/sv-bc/hm/5040.html
> > .]
> >
> > -- Brad

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Cliff Cummings - Sunburst Design, Inc.
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