RE: [sv-bc] assignment to input

Dave,

 

Where do you see that 'input bit a' or 'input real a' defaults to
variable?

 

The only sentence I see says that, "For input and inout ports, if the
port kind is omitted, then the port shall default to a net of net type
wire."

 

Thanks,

Shalom

 

________________________________

From: Rich, Dave [mailto:Dave_Rich@mentor.com] 
Sent: Monday, September 04, 2006 9:07 PM
To: Bresticker, Shalom; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] assignment to input

 

Prior to IEEE 1800-2005, input logic a, defaulted to a variable, which
meant it could not be coerced to an inout. Now it defaults to a wire of
type logic. 

 

However, input bit a, or input real a still does default to a variable
since we do not allow these types on wires.

 

As I said earlier, I don't like this new default.

 

input a has always defaulted to a wire. Now it defaults to a wire of
type logic.

 

Dave