RE: [sv-bc] 19.12.5: array of instances connection to packed array port

>From: "Feldman, Yulik" <yulik.feldman@intel.com>

>Once such notion is defined, the bit mapping between the original type
>and the vector will also be needed to be defined, in both directions.
>This will help in understanding how the ports of arrays of instances are
>mapped.

I think the existing LRM text defines it already.


>Note that there can be some complexities in such definition. For
>example:
>
>1. Mapping from the bit vector to the original type is ambiguous, when
>the original type contains packed unions.

I am not sure what you mean here.  I believe it is completely defined.
What do you think is ambiguous?


>2. Note every slice of the vector can be mapped to a single slice of the
>original type. For example, if we have two dimensional array
>a[1:0][1:0], which is mapped into a one-dimensional vector a'[3:0], then
>the slice a'[2:0] doesn't have direct representation using a single
>slice on "a".

Yes.  As I mentioned, this complicates attempts to describe the
behavior clearly.  The slicing that is done on the vector may not
be representable by the user in SystemVerilog code.  That makes it
hard to describe using the usual terminology.


>3. If the original type contains a packed struct with one member, should
>the slice on the vector that slices the whole struct be mapped to the
>member of the struct, or to the whole struct?

I am not sure what the distinction is that you are making here.  Can
you elaborate?  Anyway, the answer is presumably the whole struct.
If you want it to be the member, then use the member as the port
expression instead of the struct.


Steven Sharp
sharp@cadence.com