RE: [sv-bc] 19.12.5: array of instances connection to packed array port

> 
> >2. Note every slice of the vector can be mapped to a single slice of
the
> >original type. For example, if we have two dimensional array
> >a[1:0][1:0], which is mapped into a one-dimensional vector a'[3:0],
then
> >the slice a'[2:0] doesn't have direct representation using a single
> >slice on "a".
> 
> Yes.  As I mentioned, this complicates attempts to describe the
> behavior clearly.  The slicing that is done on the vector may not
> be representable by the user in SystemVerilog code.  That makes it
> hard to describe using the usual terminology.
> 

I thought about this difficulty, too.
Concatenations of bit-selects seems to be the only way
one could represent this slicing in native SV language.

Regards,
Doug