Re: [sv-bc] Re: Package export proposal

Francoise,

I am viewing an "export" as essentially a shorthand
to a VHDL alias declaration.  So in the case of
p2, we have the conceptual declaration:
    alias p1::x x;

This means that you *can* refer to just "p2::x" in other
places and have that resolve to the declaration that
originates in p1::x.  Due to package dependency rules,
we know that any such reference to p2 would require p1
to already exist (due p2's dependency on p1) so all of
this is resolvable at compile time.

Gord.

Francoise Martinolle wrote:

> Gordon, 
> 
> I read the proposal and I have a question regarding the comments for
> "p2":
> 
> package p1;
> 
>    int x,y;
> 
> endpackage
> 
>  
> 
>  
> 
> package p2;
> 
>    import p1::x;
> 
>    export p1::*;    // exports p1::x as the name "x"; 
> 
>                     // p1::x and p2::x are the same declaration
> 
> endpackage
> 
>  
>  
> 
> The comment I have problems with is: "p1::x and p2::x are the same
> declaration.
> It seems to infer that you can refer to x in package p1, as either p1::x
> or p2::x.
> 
> I do not like this. The export should only make the symbol x imported by
> p2 directly visible
> by design units importing p2.
> For example in module top I cannot refer to x as p2::x can I? Only p1::x
> is a legal
> full qualified reference for x.
> 
> 
> Francoise
>     '

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com