Re: [sv-bc] logic A[ 2'b11<<1 ]

Steven Sharp wrote:

> Where the text says [0:size-1], what does 'size' represent?  I think
> it represents the *number* that was computed from the expression, not
> the expression itself.  

Yes, I'd agree.  Can we say that in a simple Verilog expression?

> If it represented the expression itself being substituted into the
> larger expression, as Brad suggests, then things get really strange.

> Note that there are no parentheses...

True enough; thinking of this rewrite as a `define macro /is/ faithful
to the way most parsers must rewrite the generic expression 'size' into
generic array bounds (or vice-versa).  "Generic" because the expression's
final type and width won't be known until elaboration-time.  It's really
analogous to what designers must do in day-to-day edits of Verilog
expressions anyway.

So, is there a 1800-conforming generic expression for "(size)-1" which
computes the intended array size correctly in all cases?  Subtract 1'b1?
Add 1'sb1?  Nope, they have counterexamples...

If working this puzzle sends you into a state of denial, you might try to
discover where it says that bounds and index expressions are self-determined.
1364 actually says these are "integer expressions" - in one place the keyword
*integer* appears in the same sentence.  So denial might be effective here ;-)

Greg Jaxon

(Spoiler) : Scroll below for my current best answer to the puzzle
             as stated... any comments?




















logic A[ 0 : $unsigned(size) - 1 ]