RE: [sv-bc] Quick scope operator question

It is of course not just because the designers think that functions
calls in Verilog use late binding that it occurs - instead it is because
this is how they (and tasks) are defined to work (Section 12.5 of
1364-2001 (what I had handy))

The interaction of the function call of p::f2 with this base rule of
1364 is (perhaps) open to interpretation.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Mark
Hartoog
Sent: Tuesday, November 21, 2006 3:02 PM
To: Gordon Vreugdenhil; Mark Hartoog
Cc: Greg Jaxon; SV_BC List
Subject: RE: [sv-bc] Quick scope operator question

 
> So does that mean that you think that:
> 
>      package p;
>          function int f(int x);
>             return p::f2(x);
>          endfunction
>          function f2(int x);
>             return 1;
>          endfunction
>      endpackage
> 
> should be an error?
> 
> I don't.

I think you could argue this both ways. Verilog designers, who think
that functions can be called before they are declared, would expect 
this to work. 

In section 4.9 of the LRM it says user defined types can only 
be referenced before they are defined if they are first 
declared as a type by an empty typedef.