RE: [sv-bc] Quick scope operator question

 
By extending the existing Verilog rules for function look up in modules
to packages
if you change p2::f to just f, that will/should work.

 package p;
         function int f(int x);
             return f2(x);
          endfunction
          function f2(int x);
             return 1;
          endfunction
      endpackage

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Mark
Hartoog
Sent: Tuesday, November 21, 2006 6:02 PM
To: Gordon Vreugdenhil; Mark Hartoog
Cc: Greg Jaxon; SV_BC List
Subject: RE: [sv-bc] Quick scope operator question

 
> So does that mean that you think that:
> 
>      package p;
>          function int f(int x);
>             return p::f2(x);
>          endfunction
>          function f2(int x);
>             return 1;
>          endfunction
>      endpackage
> 
> should be an error?
> 
> I don't.

I think you could argue this both ways. Verilog designers, who think
that functions can be called before they are declared, would expect this
to work. 

In section 4.9 of the LRM it says user defined types can only be
referenced before they are defined if they are first declared as a type
by an empty typedef.