RE: [sv-bc] Quick scope operator question

I was thinking only for the simpler case where the function can be
resolved in the package itself;
 the package should be self contained. Is the forward simple reference
to f still considered a hierarchical reference?
 
So, if the function was in another package that is not imported or
another design unit, that would be a true hierarchical 
reference and the compiler should not find it.
 


________________________________

	From: Vreugdenhil, Gordon [mailto:gordon_vreugdenhil@mentor.com]

	Sent: Wednesday, November 22, 2006 1:01 PM
	To: Francoise Martinolle; Mark Hartoog
	Cc: Greg Jaxon; SV_BC List; Vreugdenhil, Gordon
	Subject: RE: [sv-bc] Quick scope operator question
	
	



	Francoise,
	
	It is actually a bit of an interesting question as to whether a
	"forward" bare reference to "f" should work.  "f" normally
	resolves only because task/function names are considered
	to be hierarchical references.  But hierarchical references
	are not permitted in packages.
	
	An amusing side-effect is probably that all task/function
	calls are illegal within packages..... :-)
	
	Gord.
	
	
	
	-----Original Message-----
	From: Francoise Martinolle [mailto:fm@cadence.com]
	Sent: Wed 11/22/2006 9:49 AM
	To: Mark Hartoog; Vreugdenhil, Gordon
	Cc: Greg Jaxon; SV_BC List
	Subject: RE: [sv-bc] Quick scope operator question
	
	
	By extending the existing Verilog rules for function look up in
modules
	to packages
	if you change p2::f to just f, that will/should work.
	
	 package p;
	         function int f(int x);
	             return f2(x);
	          endfunction
	          function f2(int x);
	             return 1;
	          endfunction
	      endpackage
	
	-----Original Message-----
	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of Mark
	Hartoog
	Sent: Tuesday, November 21, 2006 6:02 PM
	To: Gordon Vreugdenhil; Mark Hartoog
	Cc: Greg Jaxon; SV_BC List
	Subject: RE: [sv-bc] Quick scope operator question
	
	
	> So does that mean that you think that:
	>
	>      package p;
	>          function int f(int x);
	>             return p::f2(x);
	>          endfunction
	>          function f2(int x);
	>             return 1;
	>          endfunction
	>      endpackage
	>
	> should be an error?
	>
	> I don't.
	
	I think you could argue this both ways. Verilog designers, who
think
	that functions can be called before they are declared, would
expect this
	to work.
	
	In section 4.9 of the LRM it says user defined types can only be
	referenced before they are defined if they are first declared as
a type
	by an empty typedef.