RE: [sv-bc] part selects on arbitrary expressions

I don't agree. The parentheses turn the identifier inside into an
expression. So a[2] is legal, whereas today a[2] is not. (a) is not the
same as a, it is an expression whose value and, to a certain degree,
type are the same as those of a.

Note that there is a precedent for looking at something as an [N-1:0]
packed array. 1800 does it with packed structures in 4.11.

Regarding assignment size(LHS) > size(RHS), a frequent case is 
c = a + b or
c = a * b,
where a and b are N bits, and C needs to be more.

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Feldman, Yulik
> Sent: Tuesday, February 20, 2007 8:09 PM
> To: Jonathan Bromley; sv-bc@server.eda.org
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> Yes, as I wrote in the original mail, I think most operators,
including
> concatenations, should have a packed array type with [N-1:0] range;
just
> as you suggested.
> 
> W.r.t. the parenthesis, they are a syntactic wrapper in Verilog, and
> there is no reason to change that. So, both a[3:0] and (a)[3:0] in
your
> example should be illegal.

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