RE: [sv-bc] part selects on arbitrary expressions

 

 

-----Original Message-----
From: Bresticker, Shalom 
Sent: Sunday, February 25, 2007 9:27 AM
To: Feldman, Yulik; sv-bc@server.eda.org
Subject: RE: [sv-bc] part selects on arbitrary expressions

 

I don't agree. The parentheses turn the identifier inside into an
expression.

[Yulik] I'm not sure I follow you. In my eyes, an identifier placed in a
syntactical context where an expression is expected is an expression,
even if it not surrounded by parenthesis. 

 So a[2] is legal, whereas today a[2] is not. 

[Yulik] Apparently, you forgot to put the parenthesis in one of these,
so I'm not sure what exactly you meant.

(a) is not the same as a, it is an expression whose value and, to a
certain degree, type are the same as those of a.

[Yulik] What exactly the differences are and where it is defined in the
LRM? I understand that sometimes the syntax requires the presence of
parenthesis to avoid ambiguities, but I see that as a purely syntactical
issue; not semantic. To be more exact, I expect both the value and the
type of the "parenthesis expression" to be exactly the same as those of
its "operand" (not "to a certain degree"). If you show an example where
this is not the case, I would agree that the parenthesis have a special
semantic meaning.

 

Note that there is a precedent for looking at something as an [N-1:0]
packed array. 1800 does it with packed structures in 4.11.

 

Regarding assignment size(LHS) > size(RHS), a frequent case is 

c = a + b or

c = a * b,

where a and b are N bits, and C needs to be more.

[Yulik] Sure, but if "a" and "b" are not wide enough to hold the
significant bits of the result ("c"), I would suggest the designer to
make them wider and still keep the "size(LHS)=size(RHS)" property,
rather than to rely on Verilog's ability to extend RHS automatically. I
believe the methodology of keeping the "size(LHS)=size(RHS)" property by
design and letting the compiler/lint tool to warn on inadvertent
mismatches should result in less bugs than allowing the different sizes
and intermixing the intentional and unintentional mismatches without the
ability to differentiate between them automatically. But this point is,
of course, unrelated to the primary issue discussed in this thread.

 

Shalom

 

> -----Original Message-----

> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On

> Behalf Of Feldman, Yulik

> Sent: Tuesday, February 20, 2007 8:09 PM

> To: Jonathan Bromley; sv-bc@server.eda.org

> Subject: RE: [sv-bc] part selects on arbitrary expressions

> 

> Yes, as I wrote in the original mail, I think most operators,
including

> concatenations, should have a packed array type with [N-1:0] range;
just

> as you suggested.

> 

> W.r.t. the parenthesis, they are a syntactic wrapper in Verilog, and

> there is no reason to change that. So, both a[3:0] and (a)[3:0] in
your

> example should be illegal.

 


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