RE: [sv-bc] Are modport port directions enforced?

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Wed Feb 28 2007 - 10:44:17 PST
Dave Rich wrote:

> no one can make an assignment
> to variable declared as an output in the modport of a connected
> interface port except from that connected module.

I think I agree entirely with Dave's analysis.  Unfortunately,
only one of the major simulators currently enforces this.


It's interesting to note that this restriction allows me to 
enforce the "singleton modport" behaviour that I craved in my 
DVCon paper (a modport that can tolerate at most one connected 
module); I need only create a modport that declares as "output" 
a variable in the interface.  Multiple connected module 
instances would represent multiple continuous drivers on that 
variable, and would thus represent an elaboration-time error.
Thanks to Don Mills who pointed out this possibility to me
during DVCon - I had completely overlooked it.

I can see no reason why the semantics of modport direction
should not be defined in terms of a continuous assign across
the modport boundary for output and input ports, and port
collapsing for inouts.  Others have pointed out that continuous
assignment is a copy operation that can have arbitrary 
ordering with respect to other operations on its target net or
variable.  However, an ordering that gives the same visible 
results as direct writing to the target would nevertheless be 
legal; so it remains possible for simulators to optimise away 
any extra variables that might be created by following such a 
definition.  Such a "reference model" of continuous assign or 
port collapsing provides a useful way to reason about what 
operations are legal on variables and nets connected to the 
two sides of a modport.
-- 
Jonathan Bromley, Consultant

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Received on Wed Feb 28 10:44:50 2007

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