Dave, > I hope that I never see anyone depend on the static value of > a function name, or the static value of output arguments > to tasks and functions. The implied chastisement is understood and accepted :-) I couldn't agree more with you, but there's no doubt that the static nature of Verilog tasks and functions *could* be put to good use, with enough care. So people did it, and for my own part as a trainer I have always tried to be as clear- headed as possible about it with students; there's no point in skating over something that's out there and represents a serious trap for the unwary. In practice, I have always avoided relying on the static value of a function name, or of task arguments; it's just too opaque for my taste. Static local variables in a subprogram, though, are valuable in traditional Verilog. > It too bad we can't switch the default lifetime to automatic. It *is*, for classes; and we can easily declare programs to be automatic. So it's feasible and appropriate to move forward cleanly, once you've embraced the brave new software-like world. "Everything is static" was a key unifying principle of Verilog; much of what I found difficult about the language suddenly became clear once I'd grasped that. One of the real strengths of SV is that it's contrived to build its dynamic universe on top of that Verilog heritage whilst retaining full backward compatibility. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Mar 1 07:59:28 2007
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