RE: [sv-bc] Are modport port directions enforced?

> -----Original Message-----
> From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com]
> Sent: Wednesday, February 28, 2007 9:21 AM
> To: Francoise Martinolle; Rich, Dave; Steven Sharp;
> Mark.Hartoog@synopsys.COM; sv-bc@eda-stds.org
> Subject: RE: [sv-bc] Are modport port directions enforced?
> 
> > Can a task present in a modport be able to access in *any way* any
> > interface variable or
> > is the access restricted by the modport directions for the
> > variables if
> > present in the modport?
> 
> This is an area where the LRM is silent. I think we have discussed
> this in the past and decided that maybe this restriction would apply
> to some synthesis tools, but it was not a general restriction.
> 
> It does mean that if you call a interface function from a always_comb
> block, that the always_comb block can becomes sensitive to an
interface
> variable that the modport says the module does not have access to.

I believe the intent was captured in section 20.9 "access by port
reference is limited to only objects listed in the modport..." The
modport does not limit access by other mechanisms besides via port
reference.

The one driver restriction is a global rule: only one continuous driver
(implied or explicit) on a variable, regardless of the access mechanism.


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