RE: [sv-bc] part selects on arbitrary expressions

I think those last two bullets are contradictory.

 

Shalom

 

*      The parenthesis "()" in Verilog is a kind of syntactic sugaring,
in a sense that the type of the ()'s "result" is always exactly the same
as the type of its "operand". The "operand" of () is always
context-determined. 

*      The syntax of (expr)[a][b][c] for the part select operator (where
the parenthesis may be optional for certain kinds of selected
expression) seem to be the most succinct and flexible syntax suggested,
even though several committee members raised concerns about ability of
an uninformed reader to infer that the "first operand" of the part
select given in such syntax ("(expr)") is self-determined. 


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