RE: [sv-bc] part selects on arbitrary expressions

Examples from 1364 are not good, as 1364 didn't make distinction between
packed and unpacked arrays and didn't define type compatibility rules.
The syntax of arrays in Verilog resembles the syntax of unpacked arrays
in SystemVerilog, but that doesn't mean that the examples in 1364 should
be considered as referring to SV unpacked arrays with their type
compatibility rules. 

I may understand that for 1800 to be backward compatible with 1364 4.9's
"An element can be assigned a value in a single assignment", the
definition in 1800 should be that selection of a single element is of
type of the element, but this needs to be clearly defined, to be
understood by the LRM reader.

Moreover, 1364 is silent on whether a one-element part select of an
array (a[0:0]) is considered a "partial selection" or selection of a
single element, and as such it is not clear whether it is legal in 1364.
If it is not legal, then there is no backward compatibility issue with
such selection in 1800, and so 1800 is free to define it as being a
one-element array, if it wishes so. So, even if bit selection's
intention may be implied from 1364, part select's intention is still not
clear.

In fact, I think the type of a[0:0] should be defined as being a
one-element array, and not as the type of the element, to make it
possible to write parameterized code as following:

parameter MSB = ...;
parameter LSB = ...;
bit a [MSB:LSB];
assign a = b[MSB:LSB];

If the type of "b[MSB:LSB]" would change depending on whether MSB equals
to LSB or not, it would be much less convenient to define an assignment
compatible "a".

--Yulik.

-----Original Message-----
From: Bresticker, Shalom 
Sent: Sunday, March 11, 2007 5:24 PM
To: Feldman, Yulik
Cc: 'sv-bc@server.eda.org'
Subject: RE: [sv-bc] part selects on arbitrary expressions

Try 1364-2005, 4.9.3.1.2.

Shalom


> -----Original Message-----
> From: Feldman, Yulik
> Sent: Sunday, March 11, 2007 5:19 PM
> To: Bresticker, Shalom
> Cc: 'sv-bc@server.eda.org'
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> Well,
> 
> 1. It is not clear until it is clearly specified by the LRM.
> 2. It is not clear to me.
> 3. I'm not sure the LRM is full of such examples (selecting one
> element of an unpacked array and assigning it in a questionable
> context). At least I can not quickly find such an example.
> 
> --Yulik.
> 
> -----Original Message-----
> From: Bresticker, Shalom
> Sent: Sunday, March 11, 2007 5:10 PM
> To: Feldman, Yulik
> Cc: 'sv-bc@server.eda.org'
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> I repeat, you have always been able to do this. It is clear that the
> selection of a single element of an array is the type of the element.
> The LRMs are full of this.
> 
> Shalom
> 
> > -----Original Message-----
> > From: Feldman, Yulik
> > Sent: Sunday, March 11, 2007 5:07 PM
> > To: Bresticker, Shalom
> > Cc: 'sv-bc@server.eda.org'
> > Subject: RE: [sv-bc] part selects on arbitrary expressions
> >
> > Note that "b" is an unpacked array. A one-element unpacked array is
> > not assignment compatible to the type of the element of the array.
> The
> > question is whether the type of "b[0]" and "b[0:0]" is a one-element
> > unpacked array or the type of the element itself.
> >
> > --Yulik.
> >
> > -----Original Message-----
> > From: Bresticker, Shalom
> > Sent: Sunday, March 11, 2007 4:51 PM
> > To: Feldman, Yulik
> > Cc: 'sv-bc@server.eda.org'
> > Subject: RE: [sv-bc] part selects on arbitrary expressions
> >
> > These have always been legal, even in Verilog-1995. Just replace
> 'bit'
> > by 'reg'.
> >
> > > bit a;
> > > bit b [1:0];
> > > assign a = b[0];
> > >
> > > A similar issue is with part selects, selecting one element only:
> > >
> > > assign a = b[0:0];

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