Re: [sv-bc] part selects on arbitrary expressions

What should be displayed for the following simple test case?

//    6 6 4 ?
//    0 6 4 ?
//  17 17 4 ?
module test;
   logic [7:0] unpacked_array [17:11];
   logic [17:11] [7:0] packed_array;
   logic [3:7] bit_vector1;
   logic [7:3] bit_vector2;
   localparam U = $left(type(unpacked_array[17:11]));
   localparam P = $left(type(  packed_array[17:11]));
   localparam A = $left(type(bit_vector1+bit_vector2));
   initial $display(U,P,A);
endmodule

Until the LRM clearly specifies the values of the parameters U, P and A,
we shouldn't be adding more complications.

[ In reply to http://www.eda-stds.org/sv-bc/hm/5684.html .]


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