RE: [sv-bc] P1800 draft2 review : Sec 9 Processes

Sometimes 'always_comb' is safer than 'assign', as described in
 
    http://www.eda-stds.org/sv-bc/hm/3586.html
 
-- Brad
 
[ In reply to http://www.eda-stds.org/sv-bc/hm/5830.html . ]

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Michael (Mac) McNamara
Sent: Monday, April 16, 2007 1:39 PM
To: Bresticker, Shalom; Gran, Alex; sv-bc@eda-stds.org
Subject: RE: [sv-bc] P1800 draft2 review : Sec 9 Processes


The declarative assign statement is also quite good at generating
combinatorial logic.


________________________________

	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of Bresticker, Shalom
	Sent: Monday, April 16, 2007 6:16 AM
	To: Gran, Alex; sv-bc@eda-stds.org
	Subject: RE: [sv-bc] P1800 draft2 review : Sec 9 Processes
	
	

	Hi,

	 

	9.1.2.2

	    This is a rather nit-picky thing.  Section 9.1.2.2 contains
the sentence "SystemVerilog provides a special always_comb procedure for
modeling combinational logic behavior."

	      What makes always_comb so special, does it think its
better than all the other types of processes? :-)

	     I think this sentence made more sense in 1800-2005 as way
of stating that always_comb was only in SV, not in plain old Verilog,
but in the merged document shouldn't all procedures be created equal?

	 

	[SB] Nope. always_comb is specially tailored for combinational
logic. You can use a plain always, but always_comb is recommended.
'special' means 'special purpose' or 'specialized'.

	 

	 

	 


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