Date: Thu Apr 19 2007 - 07:47:30 PDT
Here are my comments. --- SB1-1-1 --------------- 1.2: Delete "Informative delay model for SDF". --- SB1-1-2 --------------- 1.4: Delete "If the name of any category starts with an italicized part, it is equivalent to the category name without the italicized part. The italicized part is intended to convey some semantic information. For example, "msb_index" and "lsb_index" are equivalent to "index." It applies only in the VCD file syntax description, which is not part of Annex A anyway. --- SB1-1-3 --------------- 1.6: "Clause 25 describes user-defined packages, compilation units ($unit), and built-in packages.": $unit is described in 3.8.1. --- SB1-1-4 --------------- 1.6: "Annex G (normative) describes the SystemVerilog standard packages, containing type definitions for mailbox, semaphore, randomize, and process." -> should be "package". Only one package, Std, is described. --- SB1-1-5 --------------- 1.8: Delete 'several' in "Several small SystemVerilog code examples are shown throughout this standard.": 'several' sounds like just a few. It is probably several hundred. --- SB1-2-1 --------------- In the Normative References (Clause 2): IEEE Std 1364(tm), IEEE Standard for Verilog(r) Hardware Description Language. IEEE Std 1364(tm)-2005, IEEE Standard for Verilog Hardware Description Language. IEEE Std 1364(tm)-2001, IEEE Standard for Verilog Hardware Description Language. IEEE Std 1800(tm), IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language. IEEE Std 1800(tm)-2005, IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language. Delete the references to 1364 and 1800 without years. Delete 1364-2001 or move it before 1364-2005. --- SB1-3-1 --------------- 3.7: Delete "A list of building block instances is referred to as a netlist." This is too big a generalization of the term netlist, and it is not used elsewhere except in one example in 3.7 where it is really is a gate-level description. --- SB1-3-2 --------------- 3.7: That same example contains the line: "not g1(sel_n, a, sel);". That looks like a mistake. A not gate has one input and one or more outputs, and a is an input to the module. Change to "not g1(sel_n, sel);". --- SB1-3-3 --------------- 3.1: "A design element is a SystemVerilog module (see Clause 22), program (see Clause 22), interface (see Clause 24), package (see Clause 25), primitive (see Clause 27) or configuration (see Clause 31)." - If config is a design element, then it needs an overview description in clause 3. --- SB1-5-1 --------------- 5.1: Change "- String" to "String literal". --- SB1-5-2 --------------- In 5.6.1, "The use of x and z in defining the value of a number is case insensitive," z should not be blue or underlined. --- SB1-5-3 --------------- 5.7 (Simulation time units and precision) is out of place in a clause on lexical conventions. Presumably, it was placed here because 5.8 is Time literals, to define time beforehand. That is not good enough justification. Move 5.7 to clause 4 (Scheduling semantics), since scheduling and time are related. --- SB1-5-4 --------------- 5.9 starts, 'A string literal is a sequence of characters enclosed by double quotes ("").' The next sentence starts, "A string literal is enclosed in quotes...," which is duplication. Delete the second phrase. --- SB1-5-5 --------------- In Table 5-1, change "b\a" to "\a". --- SB1-5-6 --------------- Delete "NOTE-the special string characters \v, \f, \a and \x were added in IEEE 1800-2005" following Table 5-1. No need for it. --- SB1-6-1 --------------- 6.1 is called Value set, but its introductory paragraph is important enough and different enough (it does not talk about value sets), that it should be a separate sub-section 6.1 called "Data objects and data types", with "Value set" being 6.2. --- SB1-6-2 --------------- 6.2: "A singular variable or expression represents a single value, symbols, or handle." -> "symbol". --- SB1-6-3 --------------- 6.14 and 7.6 both describe strings. Merge them or have only a two-sentence paragraph in 6.14 as done with classes in 6.13. --- SB1-7-1 --------------- In Clause 7, delete the first sentence, "This clause defines structures, unions and arrays, which can represent aggregate collections of data." It duplicates the following paragraph. --- SB1-7-2 --------------- 7.1.1.1 brings me to say that I dislike going down to 4th level sub-clauses if it can be avoided. Change the following structure: 7.1 Structures and unions 7.1.1 Structures 7.1.2 Unions to simply 7.1 Structures 7.2 Unions --- SB1-10-1 --------------- 10.5.1: Stu asked: Does the result of a continuous assignment to a variable update immediately when the variable is released? It should, in order to be consistent with the behavior of continuous assignments. --- SB1-10-2 --------------- A better place for 10.7 (Assignment Patterns) is in clause 7 (structures and arrays). --- SB1-11-1 --------------- 11.2.7: Define here the new term "procedural assignment operator", which Stu has invented and used in 10.3 and 10.3.1. --- SB1-11-2 --------------- 11.2.18: "If cond_predicate is true, the operator returns the first expression; if false, it returns the second expression." Brad wrote, "Actually, it evaluates an expression and returns its value." --- SB1-11-3 --------------- 11.2.18: "If the lengths of the first and second expression are different, the shorter operand shall be lengthened to match the longer and zero-filled from the left (the high-order end)," Stu asked, "Is the shorter operand always zero extended, or can it be sign extended?" It can be sign-extended, see Mantis 1004. --- SB1-11-4 --------------- 11.6.1 (String literal expressions) should not be a subsection of 11.6 (Tagged union expressions). Make it 11.7. --- SB1-12-1 --------------- Move 12.7 (Named blocks and statement labels) into 9.2 (Block statements). --- SB1-16-1 --------------- Move 16.15 (Binding) to the clause on hierarchies. --- SB1-19-1 --------------- Merge 19.4 (Display tasks) and 19.17 (Enhancements to Verilog system tasks) into Clause 20 (I/O). --- SB1-19-2 --------------- 19.9: Change "$atan2(x,y) atan2(x,y) Arc-tangent of x/y" to "$atan2(y,x) atan2(y,x) Arc-tangent of y/x", to be as in C standard. --- SB1-20-1 --------------- Move 20.4 ($sdf_annotate) into Clause 33 (SDF). --- SB1-20-2 --------------- 20.5.2.3: Change "In the $var section, a net of net type uwire shall have a variable type of wire." to "In the $var section, a net of type uwire shall have a var_type of wire." --- SB1-21-1 --------------- 21.12: Add 1800-2008 as a version_specifier and add appropriate text. Note that there is no need to have duplicate tables in 21.12 and in Annex B. For the keyword set of the current version of the LRM, it can just point to Annex B. --- SB1-21-2 --------------- 21.4.1: Change "Once a text macro name has been defined, it can be used anywhere in a source description; that is, there are no scope restrictions." to "Once a text macro name has been defined, it can be used anywhere in the compilation unit where it is defined. There are no other scope restrictions once inside the compilation unit." --- SB1-21-3 --------------- 21.4.1: "The text specified for macro text shall not be split across the following lexical tokens: ... - Strings" -> "String literals". --- SB1-22-1 --------------- 22.1: "A module can represent functional and timing at a very detailed level" -> "function". --- SB1-22-2 --------------- 22.1.1: Change "The port directions and sizes of the module" to "The direction and size of each port". --- SB1-22-3 --------------- 22.1.3: Change "The parameter type of parameters can be redefined for each instance of a module" to "Parameter types can be redefined for each instance of a module". --- SB1-22-4 --------------- 22.2: "Top-level modules are implicitly instantiated (see 22.2.1)." needs to say that the implicit instance name is the same as the module name. --- SB1-25-1 --------------- Move 25.1.1 (Built-in package) to the end of Clause 25 (Packages). Make it a 2nd-level sub-clause instead of a 3rd-level sub-clause. Add xref from 17.11 to it. --- SB1-25-2--------------- 25.1.1 says that std "contains system types (e.g., classes), variables, tasks, and functions." Actually, it only contains classes and a function. --- SB1-25-3 --------------- Add xrefs between 25.1.1 and Annex G. --- SB1-27-1 --------------- 27.1.5-6 discuss arrays of instances. Move into 22.2 (earlier than 22.2.3), as it is applicable to all kinds of modules (and interfaces). --- SB1-33-1 --------------- Move Clause 33 (SDF) to after clause 30 (Timing checks). Additional issues: 1. 3.7 and 22.2.1 define "top-level module" slightly differently. 2. 3.1: "A design element is a SystemVerilog module (see Clause 22), program (see Clause 22), interface (see Clause 24), package (see Clause 25), primitive (see Clause 27) or configuration (see Clause 31)." - 31.1 insists that a configuration is a design element, but almost of all the uses of the term within the LRM, most of which relate to timescales, are not relevant to configs. 3. 3.2 lists among the constructs modules can contain: "procedural blocks", where the reference is to always, initial, etc. procedures/constructs. Re the discussion about what to call these constructs, there are a number of places, such as here, where the term 'procedural block' is used, and it will be either awkward or unclear to just say 'procedure'. 4. String literals are discussed in 5.9 and 11.6.1. Beyond the basic definition of a string literal, the discussion of what you can do with them is split up between these two sections roughly evenly, with some duplication and overlap. The two sections should be unified, or 5.9 should be just a minimal definition of string literals, with all further discussion in 11.6.1. 5. The discussions of string literals and string types should be much closer to each other, since they are so closely related. 6. 'Nonprinting and other special characters are preceded with a backslash.': Does this mean that it is allowed to enter a nonprinting character directly (preceded by a backslash)? What is included in 'other special characters'? Is the intent of both of these only those characters in Table 5-1? What about other special characters? 7. Clause 6 is Data Types. 6.1 starts off nicely with "SystemVerilog makes a distinction between an object and its data type, etc." However, later on, the LRM blurs this distinction in terminology between objects and types. 6.3 is bad in particular, saying "There are two main groups of data types: the variable data types and the net data types." The term 'net data type' only appears 3 times, but 'net type' appears many times. I think we should be consistent and change most of the references to them to be 'net objects' or simply 'nets'. Same for 'variable data types' and 'variable types'. 8. 10.7 Assignment Patterns: Combine with 5.10-11 Structure and Array literals 9. The term 'assignment operator' is not used consistently in the LRM. It is used sometimes to refer to an entire set of operators, and sometimes to refer specifically to '='. 10. 22.2.3.5 should separate the discussions of unpacked array ports and arrays of instances. The discussion of arrays of instances there should be combined with the general discussion of port connections to arrays of instances. 11. 35 ("Programming language interface (PLI and VPI) overview"): On the one hand, VPI is treated as one generation of PLI, e.g., "Verilog procedural interface routines, called VPI routines, are the third generation of the PLI," i.e., as being included in the term 'PLI'. On the other hand, it is also treated separately, as in the title of clause 35, "PLI and VPI". This seems inconsistent and confusing. Shalom -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
