Re: [sv-bc] The term "vector" in merged draft

>Why are these inconsistent?

The definition in 6.6 says that w3 below is a vector

    wire logic [10:0] [15:0] w3;

and the definition in 7.2.1 says that it's not.

The definition in 7.2.1 says that w2 below is a vector

    typedef struct packed {logic [15:0] f;} rec;
    wire rec [10:0] w2;

and the definition in 6.6 says that it's not.

It appears that a vector must definitely be a packed array.

   1)  Can a vector have multiple dimensions?

   2)  Are there restrictions on the types of its elements?

   3)  Can the type of a vector be something other than a simple
bit-vector type?

-- Brad

[ In reply to http://www.eda-stds.org/sv-bc/hm/5846.html . ]

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, April 19, 2007 4:02 AM
To: Brad Pierce; sv-bc@eda-stds.org
Subject: RE: [sv-bc] The term "vector" in merged draft

Why are these inconsistent?

Shalom


> According to 6.9.1,
> 
>     "The term simple bit vector type is used throughout this standard 
> to refer to the data types that can directly represent a 
> one-dimensional packed array of bits."
> 
> According to 7.2.1,
> 
>    "A vector is a a one-dimensional packed array."
> 
> Those are consistent with each other but inconsistent with 6.6
> 
>    "[...] is known as a scalar. Multibit data objects of these types 
> shall be declared by specifying a range, and is known as a vector.
> Vectors are packed arrays of scalars"

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