RE: [sv-bc] Table 11-23 in Merge Draft 2 is incomplete, regarding ""Bit lengths resulting from self-determined expressions"

I've added a note in the margin next to table 11-23 to capture this comment.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
> Sent: Monday, April 30, 2007 3:43 PM
> To: sv-bc@server.eda-stds.org
> Subject: [sv-bc] Table 11-23 in Merge Draft 2 is incomplete, 
> regarding ""Bit lengths resulting from self-determined expressions"
> 
> Table 11-23 defines the "Bit lengths resulting from self-determined
> expressions".  But it only defines these for the operators of Verilog.
> 
> Table 11-1 shows that there are many new operators in SystemVerilog,
> such as,
> 
>         ->  (17.4.5)
>       dist  (17.4.4)
>     inside  (11.2.20)
>   ==?, !=?  (11.2.13)
> 
> The subclause numbers above are those used in Merge Draft 2.
> 
> -- Brad
> 
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