[sv-bc] Table 11-23 in Merge Draft 2 is incomplete, regarding ""Bit lengths resulting from self-determined expressions"

Table 11-23 defines the "Bit lengths resulting from self-determined
expressions".  But it only defines these for the operators of Verilog.

Table 11-1 shows that there are many new operators in SystemVerilog,
such as,

        ->  (17.4.5)
      dist  (17.4.4)
    inside  (11.2.20)
  ==?, !=?  (11.2.13)

The subclause numbers above are those used in Merge Draft 2.

-- Brad

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