Re: [sv-bc] Request from the SV-CC

From: Clifford E. Cummings <cliffc_at_.....>
Date: Thu Jun 21 2007 - 10:45:17 PDT
Hi, Charles -

I'm sure the SV-CC has a good reason for this request but the SV-BC 
needs to understand why this is important.

Could the SV-CC explain in lay terms that even we SV-BC-types can 
understand and include an example showing why the requested feature 
makes life better for all SV users? Even if the SV-CC could explain 
at a high level why this is important to VPI applications, it would help.

Although the SV-CC gets professional SV-courtesy and attention, the 
SV-BC needs to understand why the feature should be considered.

Regards - Cliff

At 08:00 AM 6/21/2007, Charlie Dawson wrote:
>Hi SV-BC,
>
>The SV-CC has directed me, as chair of SV-CC, to request that the SV-BC
>consider adding language to the LRM requiring implementations to have a
>mapping file which will bind names to $units objects.
>
>Please let me know if this request needs further explanation.
>
>Thank you for your consideration of this matter.
>
>   -Chas
>
>--
>Charles Dawson
>Senior Engineering Manager
>NC-Verilog Team
>Cadence Design Systems, Inc.
>270 Billerica Road
>Chelmsford, MA  01824
>(978) 262 - 6273
>chas@cadence.com
>
>
>--
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----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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Received on Thu Jun 21 10:45:41 2007

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