Re: [sv-bc] uwire & wire -vs- reg

At 06:27 PM 7/3/2007, you wrote:
> >And it is just fodder for the passionate VHDL coders who are looking
> >for more reasons to block the use of Verilog at their companies.
>
>I don't think it's a goal of this technical standardization effort to
>increase the market share of Verilog/SystemVerilog vs. VHDL.

True, but I happen to agree with the VHDL crowd that there really is 
no value in changing a declaration from a wire to a reg just because 
I changed the continuous assignment into a procedural assignment.

A few years back I asked Phil Moorby why he ever invented the regs. 
Phil's response was, that when he invented Verilog, there were no 
synthesis tools and he originally thought that everything coming from 
an always block would be a register.

Considering all the other cool things that Phil did with Verilog I am 
willing to cut him some slack on this one, but it is an extreme 
annoyance in the language. Forgetting to declare the regs is still 
the most frequent mistake that I personally make and is still very 
confusing to new users. I tell users that whenever they see "illegal 
left-hand side assignment" or "illegal lvalue" or "illegal assignment 
to wire" that all of those error messages should really just say, 
"you forgot to declare your silly regs!"

I would like to think that I am a pretty productive coder, but if I 
could declare everything to be a wire or wire-bus in Verilog, my 
productivity would increase even more. Seriously!

I would like to declare everything as a wire, allow first usage to 
determine if it acts like a wire or a reg, and get an error message 
if I ever try to assign to the same wire from BOTH a continuous 
assignment and a procedural block. It's really that simple.

It would be a very friendly simplification to the Verilog language if 
permitted.

Regards - Cliff


>[ In reply to http://www.eda-stds.org/sv-bc/hm/6185.html .]
>
>-- Brad

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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