[sv-bc] Case Statement Enhancement Proposal Idea

Hi, All -

Matt - could I have time to bounce this idea off of the BC on Monday?

Don & Heath are well aware of the simple 2-to-4 decoder example that 
we use when teaching synthesis with full_case, priority case or unique case

always_comb begin
   y = '0;
   unique case ({en,a})
     3'b100: y[a]='1;
     3'b101: y[a]='1;
     3'b110: y[a]='1;
     3'b111: y[a]='1;
   endcase
end

In this example, if you remove the unique keyword, this simulates and 
synthesizes to a very efficient 2-to-4 decoder, but with the unique 
keyword, this still simulates like a 2-to-4 decoder and issues a 
run-time warning whenever en=0 and the always_comb block is executed. 
It also optimizes away the en-input to give the wrong logic when synthesized.

If the default (y = '0;) assignment could be moved to just inside of 
the case statement and always executed before testing the other case 
items, the problem would be solved.

Attached is a first-cut proposal to address this problem. If the idea 
receives favorable attention, I will take it as an action item to 
make a formal proposal.

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training

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