Hi, Brad - At 10:45 AM 7/5/2007, Brad Pierce wrote: >To get the effect of a parallel_case that is not a full_case, add a null >default to the unique-case, such as > >always_comb begin > y = '0; > unique case ({en,a}) > default; > 3'b100: y[a]='1; > 3'b101: y[a]='1; > 3'b110: y[a]='1; > 3'b111: y[a]='1; > endcase >end > >-- Brad This is a somewhat well-known trick (kill full_case equivalent by adding a case default - also kills the full_case component of unique and kills priority altogether). But there are still a couple of issues with this coding style: (1) It looks pretty silly to add an empty default to a case statement. I like the following code better: always_comb begin unique case ({en,a}) initial y = '0; // pre-default assignment 3'b100: y[a]='1; // updates 3'b101: y[a]='1; 3'b110: y[a]='1; 3'b111: y[a]='1; endcase end Note that begin-end are shown but not needed in this example because the initialization assignment is now part of the case statement. Also no silly null-default to explain to other engineers or in design reviews (because there are many engineers that do not know that adding default to a unique-case statement is synthesis-equivalent to the old parallel_case). (2) This is a small example. In recent years, as I have benchmarked dc efficiency on larger examples, and I have noted that I frequently get better synthesis results by making an initial assignment before the case statement and throwing a case-default that sets all of the variables to X's inside of the case statement. See the results from four years ago in the paper (pages 19-22): http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf I semi expect to see the same results using dc by making the case-initial assignment followed by a case-default of all X's (to be tested) The pre-default (case-initial) concept is exceptionally useful when combined with unique. I am not a big fan of priority. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jul 5 12:29:40 2007
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