I believe I understand the synthesis viewpoint here. There really isn't a simulation-synthesis mismatch. The warnings in the simulation output mean "Your logic is incorrect. It violates your assumptions and will not work the way you expect." Lo and behold, the synthesis output doesn't work the way you expected. That is not a mismatch. You just chose to ignore some of your simulator output. If users are going to ignore the simulator warnings when the unique qualifier is incorrect, and don't want synthesis tools to assume that the qualifier is correct, then there is no point to having it in the language in the first place. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 10 07:39:55 2007
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