> IMHO, it appears you may have missed the point of the request. I respectfully submit that I haven't... and I suspect Arturo was gently and justifiably poking fun at my let's-design-a-decoder-competition. > The general code case is like this: [set defaults on a bunch of signals and then, in various branches of a possibly incomplete case statement, adjust various subsets of those signals] In your/Cliff's examples, the case statement is neither 'unique' nor 'priority' because it is both possible and reasonable for no branch to be taken. As others have pointed out, synthesis optimizations can be encouraged - whilst retaining sane semantics - simply by adding an empty default branch to the unique case. With hindsight, it might have been preferable to make 'unique' assert "at most one branch" rather than "exactly one branch". The present effect of 'unique' could then be had by applying BOTH modifiers. But now we are stuck with it, and we can get "at most one branch" easily by using unique and an empty default. We don't need new syntax for something that many designers have been comfortably doing for years anyway. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jul 8 01:29:13 2007
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