> Lint tools typically do these checks, at least partly, by running > mini-synthesis of their own, and we certainly don't want simulators > doing that. Agreed. But it would be nice to have a standardised way of indicating what checks we would like performed by a tool that knows how to do them. Surely this is precisely what attributes were designed for? If we decorate a module declaration with a suitable attribute, any tool that knows how to do so could then perform the checks indicated by the attribute. Those checks are then localised to the decorated module, and could even be overridden on individual nodes: (* REPORT_UNDRIVEN=1 *) module foo (input logic a, ...); // by default, all nodes of this module are checked for being driven (* REPORT_UNLOADED=1 *) logic [7:0] some_rtl_signal; // some_rtl_signal is checked for both driven and received (* REPORT_UNDRIVEN=0 *) wire might_be_floating; // might_be_floating is not checked at all .... endmodule I'd be all in favour of standardising a few attribute names of this kind, on the basis that tools are not required to implement them, but if they do so then it must be with the standardised meaning. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jul 6 07:40:14 2007
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