[sv-bc] RE: [sv-ec] Query related to Cross Coverage

Sandeep,

Use of a wire as in the example is OK and should be allowed. The BNF was
not meant to disallow nets; it was meant to disallow general expressions
due to the naming issues. Sampling an arbitrary expression is allowed
but users must explicitly create a cover-point for the expression - and
thus give it a name. There is no semantic ambiguity sampling nets for
coverage.

Perhaps we should note this in the LRM and change variable to
signal_identifier in the BNF, and change variable to signal in the
following:

When a variable V is part of a cross coverage, SystemVerilog implicitly
creates a coverage point for the variable, as if it had been created by
the statement coverpoint V;

	Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Sandeep Dasgupta
Sent: Wednesday, July 11, 2007 3:58 AM
To: sv-ac@eda-stds.org; sv-bc@eda-stds.org; sv-ec@eda-stds.org
Subject: [sv-ec] Query related to Cross Coverage


Hi,

I have the following query  related to the cross_item construct,

Consider the test case,

module top;

 bit [3:0] a, b, c;
 reg clk;
 wire w;

 covergroup cov2 @(posedge clk);
  BC: coverpoint b+c;
  aXb : cross  BC,   w ;       <--  Usage of a wire net as cross_item.
 endgroup
endmodule

Now as per IEEE Std 1800-2005, section 18.5,
cross_item ::= cover_point_identifier
                      | variable_identifier
variable_identifier :: identifier

Now i think the usage of w (a wire net) as the cross_item (in the above 
mentioned testcase ) is illegal,
as w does not seem to  be a variable identifier.But most of the 
simulators let the testcase pass.
So please suggest what would be the ideal behaviour.


Thanks and Regards,
Sandeep Dasgupta.






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