Bresticker, Shalom wrote: > Gord, > > Thanks. A single comment: > >>> 4. Should you be able to leave off an output argument? That >> presumably >>> means simply discarding the output value. (Mantis 1600) >> GORD: I strongly prefer allowing defaults for outputs. >> Silently ignoring >> GORD: an output is very dangerous as far as I am concerned since >> GORD: the addition of a *non-defaulted* output could be missed in >> GORD: calling code. If we allow explicit defaults, then there is >> GORD: a direct mechanism for a user to add a "sink" themselves and >> GORD: ensure that outputs are only ignored when they want them to >> GORD: be. If we allow defaults to be skipped, I'll be that we end >> GORD: up adding something like "default_output_formals none" or >> GORD: similar to have a standard mechanism for disallowing such code. >> >> GORD: I almost certainly oppose silently allowing outputs to >> be unassociated. > > [SB] Verilog has always had implicitly unconnected module ports, though. > Just omit them from the port connection list. Yes - and people still have to then find floating nets after the fact when they do so accidentally. In a task/function setting, it is much less likely that the *intent* was to skip an output and it is going to be *much* harder to debug in general. Allowing a mechanism for the tf writer to *permit* outputs to be left open would be much more safe than always getting that as permissible behavior. Gord. -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 17 06:43:34 2007
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