Re: [sv-bc] Mantis 1602: task/function default inout arguments

A Verilog function is syntactic sugar for a combinational module.  The
reason port width mismatch warnings/errors are issued only for modules
is that the module/endmodule is typically the boundary in separate
compilation.

In Verilog the evaluation of the right-hand side of an assignment
depends on the width of the left-hand side.  For example, after the
following,  a!=b

    reg [1:0] a, b;
    reg [0:0] c;

        a  = 2'b11 + 2'b01 >> 1;
    {c, b} = 2'b11 + 2'b01 >> 1;

Because module port connections, like function argument passing, are
assignment-like contexts, each argument is evaluated in the context of
an assignment to the corresponding module port.  For example, if the
port widths of module M are given by a parameter N, then below m2.a[1]!=
m3.a[1].

    M m2 #(.N(2)) (.a(2'b11 + 2'b01 >> 1), .out(o));
    M m3 #(.N(3)) (.a(2'b11 + 2'b01 >> 1), .out(o));

An implementation must in general wait until the down-designs are known
and have been elaborated before the port expressions can be correctly
evaluated. Likewise, it must in general wait until the up-designs are
known and have been elaborated before the function actuals can be
correctly evaluated.  It must in general wait even to know whether an
expression is an lvalue or rvalue.  

In a separate compilation flow, tools typically do not wait, but instead
speculatively evaluate the port expressions as if they were
self-determined, and then error at link time if the width of a port does
not equal the self-determined width of its corresponding port
expression, because of the possibility that the port expression was
evaluated incorrectly and cannot simply be truncated or extended to fit.

Because of this, non-separate compilation tools typically warn when they
detect such a width mismatch, in case the user intends the code to be
separately compilable.

-- Brad

[ In reply to http://www.eda-stds.org/sv-bc/hm/6292.html .]


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