And the questions are -- should it be legal in SystemVerilog 2008 to declare default argument values for inout and output arguments of subroutines, and, if so, what should the semantics be? I think it wouldn't be good ROI to support such default argument values in SystemVerilog 2008, and, if SystemVerilog 2005 did not explicitly forbid such default arguments, then we should update the LRM to forbid them. This feature could always be added in future revs of the standard. -- Brad -----Original Message----- From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom Sent: Tuesday, July 17, 2007 11:42 AM To: Greg Jaxon Cc: sv-bc@eda.org Subject: RE: [sv-bc] Mantis 1602: task/function default inout arguments Greg, But what do you (and Brad and everyone else) think about the questions on Mantis 1602? Thanks, Shalom -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 17 12:14:42 2007
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