RE: [sv-bc] Mantis 1602: task/function default inout arguments

SV 2005 explicitly allows inout defaults. However, their semantics are
not clear. 
SV 2005 explicitly disallows output defaults.

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
> Sent: Tuesday, July 17, 2007 10:14 PM
> To: sv-bc@server.eda.org
> Subject: RE: [sv-bc] Mantis 1602: task/function default inout 
> arguments
> 
> And the questions are -- should it be legal in SystemVerilog 
> 2008 to declare default argument values for inout and output 
> arguments of subroutines, and, if so, what should the semantics be? 
> 
> I think it wouldn't be good ROI to support such default 
> argument values in SystemVerilog 2008, and, if SystemVerilog 
> 2005 did not explicitly forbid such default arguments, then 
> we should update the LRM to forbid them.
> 
> This feature could always be added in future revs of the standard.
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On 
> Behalf Of Bresticker, Shalom
> Sent: Tuesday, July 17, 2007 11:42 AM
> To: Greg Jaxon
> Cc: sv-bc@eda.org
> Subject: RE: [sv-bc] Mantis 1602: task/function default inout 
> arguments
> 
> Greg,
> 
> But what do you (and Brad and everyone else) think about the 
> questions on Mantis 1602?
> 
> Thanks,
> Shalom
> 
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