RE: [sv-bc] streaming operator: svlog LRM

hi Kapil

In your example....

Typdef Struct{
            logic a;
            logic b;
} myType
 
Typdef Struct{
            logic a;
            logic b;
            logic c;
            logic d;
} myType

I'm guessing you meant these two typedefs to have different names?
 
 
  Module test( input myType in1, input myType in2, 

and in1, in2 should be of the two different types???

    output myType out1 [1:0], output logic[3:0] out2, output out3);

            assign out1 = {>>{in1, in2}}; 
            assign out2 = {>>{in1, in2}};
            assign out3 = {>>{in1, in2}};

I think that *all* these assignments are illegal, because 
the streaming concatenation {>>{in1,in2}} contains six bits -
it's effectively {in1.a,in1.b,in2.a,in2.b,in2.c,in2.d} -
and the targets are smaller than 6 bits.  However, if you
provided a 6-bit or larger target, then the assignments 
would be fine.  The bitstream resulting from the {>>{}} 
operation is automatically cast to the type of the target.
What you *cannot* do is use the bitstream in a situation 
where it has a type of its own.  For example, if A is an
integer variable,

   A = {>>{in1, in2}} + 1;

would be illegal.

Mantis item 1707 covers this area.  I've recently written
a new proposal for it; I'd be very interested to know if
that new proposal answers your concerns.  The whole
Mantis item is at
  http://www.eda-stds.org/svdb/view.php?id=1707
(log on as username guest, password guest)

and here is the modified LRM text as a PDF for convenience.
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