[sv-bc] streaming operator: svlog LRM

Hi,

 

I was looking at the streaming operator section (8.17) in the system
verilog LRM.

 

In the LRM there are two statements:

1. The result of the pack operation can be assigned directly to any
bit-stream type variable. As defined in section 4.16, a bit-stream type
is a type consisting of the following:

- Any integral, packed, or string type

- Unpacked arrays, structures, or classes of the above types

- Dynamically sized arrays (dynamic, associative, or queues) of any of
the above types

2. The stream is not an integral value; to participate in an expression,
a cast is required. 

 

 

I am a bit confused as to what [1] and [2] would mean together. Consider
the following test case:

 

Typdef Struct{

            logic a;

            logic b;

} myType

 

Typdef Struct{

            logic a;

            logic b;

            logic c;

            logic d;

} myType

 

 

Module test(input myType in1, input myType in2, output myType out1
[1:0], output logic[3:0] out2, output out3);

            assign out1 = {>>{in1, in2}}; 

            assign out2 = {>>{in1, in2}};

            assign out3 = {>>{in1, in2}};

endmodule

 

Would all the assignment statements work? Also, what would be type of
"{>>{in1,in2}}" every time? (What does [2] mean?? - it is not an
integral value!!)

 

Thanks,

Kapil

 


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