[sv-bc] Using interface-type port in parameter override

Following up to

  http://www.eda-stds.org/svdb/view.php?id=1224
  http://www.eda-stds.org/svdb/view.php?id=1058

the following example is allowed by the BNF, and seems reasonable to me,
but is the "bot#(ifc.P)" semantically legal?


interface IFC#(parameter P = 1);
endinterface

module top(output [7:0] o, output test_bit);
  IFC#(2) ifc();
  mid mid(o, ifc);
  assign test_bit = (o == 2);
endmodule

module mid(output [7:0] o, IFC ifc);
  bot#(ifc.P) bot(o);   // <--- legal A.4.1.1 param_expression ?
endmodule

module bot#(parameter P = 3)(output [7:0] o);
  assign o = P;
endmodule


-- Brad


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