[sv-bc] time literals

The following came up in the Verilog-AMS committee.
I don't remember whether we discussed this specifically in the past.
We certainly discussed closely related issues.

Can one write:

realtime td = 1.2345ns;

# td; // as near a 1.2345ns delay as possible

If not, where does the LRM say or at least imply not?

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033


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