RE: [sv-bc] time literals

From 1800-2008 D3a   (I'm on the road and don't have easy access to my
other LRM versions)
 
 
 
A.6.2
blocking_assignment ::=

variable_lvalue = delay_or_event_control expression

A.6.5
delay_or_event_control ::=

delay_control

delay_control ::=

# delay_value

A.2.2.3
delay_value ::=

unsigned_number

| real_number

| ps_identifier

| time_literal

 
So, that seems to say value can be any of unsigned_number, real_number,
ps_identifier, time_literal
 
6.12
 
The realtime declarations shall be treated synonymously with real
declarations and can be used interchangeably.

So, as long as data type "real" is expressed as a "real_number"  I think
this is allowed.
 
 
~Alex
 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Thursday, August 30, 2007 5:26 AM
To: sv-bc
Subject: [sv-bc] time literals



The following came up in the Verilog-AMS committee. 
I don't remember whether we discussed this specifically in the past. 
We certainly discussed closely related issues. 

Can one write: 

realtime td = 1.2345ns;

# td; // as near a 1.2345ns delay as possible 

If not, where does the LRM say or at least imply not? 

Thanks, 
Shalom 

Shalom Bresticker 
Intel Jerusalem LAD DA 
+972 2 589-6852 
+972 54 721-1033 


-- 
This message has been scanned for viruses and 
dangerous content by MailScanner <http://www.mailscanner.info/> , and is

believed to be clean. 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.