Steven's point is that it works today in old Verilog code. And therefore the back-compatibility consideration means it needs to be legal. Shalom > -----Original Message----- > From: owner-sv-cc@server.eda.org > [mailto:owner-sv-cc@server.eda.org] On Behalf Of Jim Vellenga > Sent: Tuesday, September 04, 2007 11:59 PM > To: Brad Pierce; sv-bc > Cc: sv-cc@server.eda-stds.org; Steven Sharp > Subject: RE: [sv-cc] RE: [sv-bc] Need your review of Mantis item 1741 > > Yes, I believe that to be the case. Steve Sharp's comment is > perhaps a little confusing: > > "If the unnamed block is not a scope (because it doesn't > contain any local variable declarations) then the named block > name would be in the next scope out." > > Perhaps it would be clearer to say that "then the named block > _scope_ would be the next scope out." > > For a fuller test case at the language level (as opposed to > VPI), one could write > > module top; > logic x; > > initial > begin > begin : BLK > var v = 1'b1; // Is this decl contained in the unnamed begin? > end > end > > initial > #(1) x = top.BLK.v; > endmodule > > The SV-BC must decide, of course, whether or not this is legal. > > Regards, > Jim Vellenga > > --------------------------------------------------------- > James H. Vellenga 978-262-6381 > Software Architect (FAX) 978-262-6636 > Cadence Design Systems, Inc. vellenga@cadence.com > 270 Billerica Rd > Chelmsford, MA 01824-4179 > "We all work with partial information." > ---------------------------------------------------------- > > ]-----Original Message----- > ]From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On > ]Behalf Of Brad Pierce > ]Sent: Tuesday, September 04, 2007 4:34 PM > ]To: sv-bc > ]Cc: sv-cc@eda-stds.org > ]Subject: [sv-cc] RE: [sv-bc] Need your review of Mantis item > 1741 ] ]Would a hierarchical reference to BLK.v from outside > the unnamed ]begin-end be legal in the following example? > ] > ] begin > ] begin : BLK > ] var v = 1'b1; // Is this decl contained in the > unnamed begin? > ] end > ] end > ] > ]-- Brad > ] > ]-----Original Message----- > ]From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On > Behalf Of Jim ]Vellenga > ]Sent: Tuesday, September 04, 2007 1:25 PM > ]To: sv-bc > ]Cc: sv-cc@eda-stds.org > ]Subject: [sv-bc] Need your review of Mantis item 1741 ] > ]SV-BC, ] ]As directed by the Champions, I am requesting your > review of ]Mantis item > ]1741 with respect to the question of when an unnamed block > does or does ]not constitute a scope. > ] > ]In my append to 1741 of August 13, I have included a > statement from ]Steve Sharp as to the reasons why we should > consider an ]unnamed begin or ]unnamed fork to be a scope if > and only if it contains a block item ]declaration. > ] > ]Please review this soon so that we can include the revised > proposal in ]the upcoming version of the standard. > ] > ]Regards, > ]Jim Vellenga > ] > ]--------------------------------------------------------- > ]James H. Vellenga 978-262-6381 > ]Software Architect (FAX) 978-262-6636 > ]Cadence Design Systems, Inc. vellenga@cadence.com > ]270 Billerica Rd > ]Chelmsford, MA 01824-4179 > ]"We all work with partial information." > ]---------------------------------------------------------- > ] > ]-- > ]This message has been scanned for viruses and dangerous > content by ]MailScanner, and is believed to be clean. > ] > ] > ] > ]-- > ]This message has been scanned for viruses and ]dangerous > content by MailScanner, and is ]believed to be clean. > ] > ] > ] > > -- > This message has been scanned for viruses and dangerous > content by MailScanner, and is believed to be clean. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Sep 4 14:01:59 2007
This archive was generated by hypermail 2.1.8 : Tue Sep 04 2007 - 14:02:06 PDT