Re: [sv-cc] RE: [sv-bc] Need your review of Mantis item 1741

I agree with Steven that the example that you note should
be legal.

Note that there are some slightly subtle differences.

Here is a "task" based example that illustrates what I think
are the correct implications:

module top;
   task t;
    integer x;
    begin : BLK
       integer y;
    end
   endtask

   initial t.BLK.y = 1;
endmodule


Legal -- BLK is in the scope of "t".



module top;
   task t;
    integer x;
    begin           // call this OUTER
      begin : BLK
         integer y;
      end
    end
   endtask

   initial t.BLK.y = 1;
endmodule


This is legal since OUTER is an unnamed block and the parent
scope is "t" so BLK is considered to be in "t".




module top;
   task t;
    begin           // call this OUTER
      integer x;
      begin : BLK
         integer y;
      end
    end
   endtask

   initial t.BLK.y = 1;
endmodule


This is not legal since the "begin" here is an unnamed
block containing a declaration.



The last one is a bit annoying but likely unavoidable -- someone
could easily reverse the lines "begin" and "integer x"
and assume that it is still "Verilog".  But 1364 doesn't
allow such forms; the "integer x" would have to precede
the "begin".  That is a somewhat subtle distinction that
one could easily miss and wonder why 1800 "broke Verilog".

Gord.



Jim Vellenga wrote:
> Yes, I believe that to be the case.  Steve Sharp's comment
> is perhaps a little confusing:
> 
> "If the unnamed block is not a scope (because it doesn't contain any
> local variable declarations) then the named block name would be in
> the next scope out."
> 
> Perhaps it would be clearer to say that "then the named block _scope_
> would be the next scope out."
> 
> For a fuller test case at the language level (as opposed to VPI),
> one could write
> 
> module top;
>   logic x;
> 
>   initial
>     begin
>       begin : BLK
>         var v = 1'b1;  // Is this decl contained in the unnamed begin?
>       end
>     end
> 
>   initial
>     #(1) x = top.BLK.v;
> endmodule
> 
> The SV-BC must decide, of course, whether or not this is legal.
> 
> Regards,
> Jim Vellenga
> 
> --------------------------------------------------------- 
> James H. Vellenga                            978-262-6381 
> Software Architect                              (FAX) 978-262-6636 
> Cadence Design Systems, Inc.         vellenga@cadence.com 
> 270 Billerica Rd
> Chelmsford, MA 01824-4179
> "We all work with partial information." 
> ----------------------------------------------------------  
> 
> ]-----Original Message-----
> ]From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
> ]Behalf Of Brad Pierce
> ]Sent: Tuesday, September 04, 2007 4:34 PM
> ]To: sv-bc
> ]Cc: sv-cc@eda-stds.org
> ]Subject: [sv-cc] RE: [sv-bc] Need your review of Mantis item 1741
> ]
> ]Would a hierarchical reference to BLK.v from outside the unnamed
> ]begin-end be legal in the following example?
> ]
> ]    begin
> ]      begin : BLK
> ]        var v = 1'b1;  // Is this decl contained in the unnamed begin?
> ]      end
> ]    end
> ] 
> ]-- Brad
> ]
> ]-----Original Message-----
> ]From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Jim
> ]Vellenga
> ]Sent: Tuesday, September 04, 2007 1:25 PM
> ]To: sv-bc
> ]Cc: sv-cc@eda-stds.org
> ]Subject: [sv-bc] Need your review of Mantis item 1741
> ]
> ]SV-BC,
> ]
> ]As directed by the Champions, I am requesting your review of 
> ]Mantis item
> ]1741 with respect to the question of when an unnamed block does or does
> ]not constitute a scope.
> ]
> ]In my append to 1741 of August 13, I have included a statement from
> ]Steve Sharp as to the reasons why we should consider an 
> ]unnamed begin or
> ]unnamed fork to be a scope if and only if it contains a block item
> ]declaration.
> ]
> ]Please review this soon so that we can include the revised proposal in
> ]the upcoming version of the standard.
> ]
> ]Regards,
> ]Jim Vellenga 
> ]
> ]--------------------------------------------------------- 
> ]James H. Vellenga                            978-262-6381 
> ]Software Architect                              (FAX) 978-262-6636 
> ]Cadence Design Systems, Inc.         vellenga@cadence.com 
> ]270 Billerica Rd
> ]Chelmsford, MA 01824-4179
> ]"We all work with partial information." 
> ]---------------------------------------------------------- 
> ]
> ]--
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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