>From: "Brad Pierce" <Brad.Pierce@synopsys.com> >Would a hierarchical reference to BLK.v from outside the unnamed >begin-end be legal in the following example? > > begin > begin : BLK > var v = 1'b1; // Is this decl contained in the unnamed begin? > end > end Yes, it would. Note that if the initializer were removed, and 'var' were replaced with 'reg', this would be valid Verilog-1995 code. The hierarchical reference was legal there, so it must be legal in SV also. Block names did not cause surrounding unnamed blocks to become scopes in Verilog, so they must not do so in SV. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sat Sep 8 07:11:19 2007
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