Re: [sv-bc] Need your review of Mantis item 1741

As discussed in

    http://www.eda-stds.org/sv/sv-champions/hm/0189.html

doesn't that unnamed block contain local variable declarations?  Doesn't
the largest of a set of matryoshka dolls contain even the smallest? 

-- Brad

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com] 
Sent: Saturday, September 08, 2007 7:11 AM
To: sv-bc@eda-stds.org; Brad.Pierce@synopsys.COM
Cc: sv-cc@eda-stds.org
Subject: RE: [sv-bc] Need your review of Mantis item 1741


>From: "Brad Pierce" <Brad.Pierce@synopsys.com>

>Would a hierarchical reference to BLK.v from outside the unnamed 
>begin-end be legal in the following example?
>
>    begin
>      begin : BLK
>        var v = 1'b1;  // Is this decl contained in the unnamed begin?
>      end
>    end

Yes, it would.  Note that if the initializer were removed, and 'var'
were replaced with 'reg', this would be valid Verilog-1995 code.  The
hierarchical reference was legal there, so it must be legal in SV also.
Block names did not cause surrounding unnamed blocks to become scopes in
Verilog, so they must not do so in SV.

Steven Sharp
sharp@cadence.com


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