RE: [sv-bc] Resolving name resolution

Gord and I have had an offline email exchange about name
resolution.

What it basically comes down to is Gord find situations
like this:

  function void f (int x);
      some_object.randomize with (x < y);

fundamentally different from other situations in Verilog
or System Verilog where names cannot be resolved until
elaboration. I find this situation not really all that
different from the system verilog code:

   parameter type T = ....
   T x;
   initial x.y = 1;

where 'y' cannot be resolved until elaboration, or the V2k code:

parameter p = 1;
generate 
if (1) begin : A
  if (1) begin : B
     initial $display("%m A.x =", A.x);
     if (p == 1) begin : A
        int x = 1;
     end
  end
  int x = 2;
end
endgenerate

Here 'A.x' cannot be resolved until after elaboration.

I will let Gord defend his position. My position is that these
situations
are really not that different. If we had the standard to do over again,
I would
probably vote for a different randomize with syntax, but this is now
part of an 
approved standard and customers are writing code this way. If this were
unimplementable,
I think we could justify making a language change that was not backwards

compatible, but it is not unimplementable. I have not seen any other
proposal
to 'fix' this issue which is backwards compatible with P1800. 

Mark Hartoog


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