RE: [sv-bc] Assignment compatibility after elaboration

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Wed Sep 05 2007 - 12:55:19 PDT
Greg, 

> > Do you have a case where it would matter to a synthesis tool?
> 
> Yes.  Are they rare?  Once you adopt a coding style that 
> relies on type parameters or types declared in interfaces, 
> this issue comes up immediately.

At least for type parameters, it was explained that it should not be a
problem.

> Is the module-specialization forest something that a 
> testbench compiler can reconstruct from all the trees of a 
> fully instantiated design?  If that is hopeless, then perhaps 
> the LRM is serving testbench needs here.
> I'd find that argument hard to believe, but I'm not a 
> testbench expert.

On the contrary, I was saying that while the effect on synthesizable
code might be small, it could make writing testbenches much more
difficult. 

On the other hand, SV verification has caught on much more than SV
design, and I have not heard that this has been one of the bigger
problems.

Shalom

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Received on Fri Sep 7 15:31:49 2007

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