Re: [sv-bc] Assignment compatibility after elaboration

From: Greg Jaxon <Greg.Jaxon_at_.....>
Date: Wed Sep 05 2007 - 14:32:17 PDT
Bresticker, Shalom wrote:
> Greg, 
> 
>>> Do you have a case where it would matter to a synthesis tool?
>> Yes.  Are they rare?  Once you adopt a coding style that 
>> relies on type parameters or types declared in interfaces, 
>> this issue comes up immediately.
> 
> At least for type parameters, it was explained that it should not be a
> problem.

??

>> Is the module-specialization forest something that a 
>> testbench compiler can reconstruct from all the trees of a 
>> fully instantiated design?  If that is hopeless, then perhaps 
>> the LRM is serving testbench needs here.
>> I'd find that argument hard to believe, but I'm not a 
>> testbench expert.
> 
> On the contrary, I was saying that while the effect on synthesizable
> code might be small, it could make writing testbenches much more
> difficult. 

In other words, no one wants instance-specificity - it distinguishes
too many types whose provenance is otherwise identical.

> On the other hand, SV verification has caught on much more than SV
> design, and I have not heard that this has been one of the bigger
> problems.

What semantics does it provide?  Notice how type parameters are
the easiest way to find out...

Greg


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Fri Sep 7 15:43:38 2007

This archive was generated by hypermail 2.1.8 : Fri Sep 07 2007 - 15:44:17 PDT