[sv-bc] attribute syntax

I was looking at Mantis 1450.

5.12 says,

"An attribute_instance can appear in the SystemVerilog description as a
prefix attached to a declaration, a module item, a statement, or a port
connection. It can appear as a suffix to an operator or a function name
in an expression."

The syntax in A.8.3 says,

"inc_or_dec_expression ::=
	  inc_or_dec_operator { attribute_instance } variable_lvalue
	| variable_lvalue { attribute_instance } inc_or_dec_operator"

The placement of attribute_instance in the last line seems inconsistent
with the text.

More generally, I suspect we (and the other sub-committees and the
champions) have been negligent about putting in { attribute_instance }
everywhere it should be in all the BNF changes we have made. I know I
have not given them any thought.

Frankly, I think they are a big pain in the neck in the BNF. I'd be in
favor of simply removing them everywhere from the BNF and just leaving
the textual description of where they can appear.

Thanks,
Shalom



Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033

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