RE: [sv-bc] RESEND: Default Module Ports Proposal posted

Good point.

Shalom 

> -----Original Message-----
> From: Greg Jaxon [mailto:Greg.Jaxon@synopsys.com] 
> Sent: Monday, October 01, 2007 9:04 PM
> To: Bresticker, Shalom
> Cc: mills@lcdm-eng.com; sv-bc@eda.org
> Subject: Re: [sv-bc] RESEND: Default Module Ports Proposal posted
> 
> Bresticker, Shalom wrote:
> > Maybe more comprehensive would be to say something to the 
> effect that 
> > the default is as though explicitly written in the 
> instantiation. That 
> > would also answer questions like size extension, signing, etc.
> 
> That would be the wrong direction to send the reader.  Names 
> in the default expression do not resolve in the instantiation's scope.
> 
> Greg
> 
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.